Flow control mechanisms in computer networks govern the transfer of packets from a source node to a destination node. Typical flow control mechanisms include wiring and logic to handle multiple packets arriving concurrently at the destination node. There are several drawbacks with such mechanisms.
First, if the destination node can simultaneously process fewer packets than can arrive in a clock cycle, additional hardware may be required to buffer the arriving packets until the destination node can process them. Alternatively, the destination node may be able to process as many packets simultaneously as can arrive in a cycle, again requiring significant additional hardware. This additional hardware poses a particular problem on semiconductor chips where space is extremely limited.
Second, arbitration logic may be required at the destination node to determine an order to accept the packets. In addition to increasing the complexity of the logic, the packet latency may significantly increase due to the arbitration. Instead of a packet being accepted during the clock cycle that it arrives, the packet has to wait. As a result, the overall performance of the system is reduced.
In ring topologies, concurrent multiple packet arrival is a particular concern. If a packet has to wait on a ring until the destination node accepts the packet, packets behind the waiting packet may be blocked from advancing on the ring. As a result, unnecessary congestion can occur at the destination node. This condition significantly increases packet latency and reduces peak throughput of the ring.
Accordingly, there is a need in the art to overcome the drawbacks caused by concurrent multiple packet arrival, particularly in ring topologies.